參數(shù)資料
型號(hào)： MC68HCL05C8AB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SHRINK, PLASTIC, DIP-42
文件頁數(shù)： 160/166頁
文件大?。?/td> 1914K
代理商： MC68HCL05C8AB
Serial Peripheral Interface (SPI)
SPI Registers
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
Technical Data
MOTOROLA
Serial Peripheral Interface (SPI)
93
10.6.1 Serial Peripheral Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
Address: $000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
相關(guān)PDF資料
PDF描述
MC68HSC05C8CFB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
MC68HC05C8AMB 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HSC05C8AB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
MC68HC05C8CFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC05C8MFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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