參數(shù)資料
型號: MC68HCL05J1ADW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 76/128頁
文件大?。?/td> 1650K
代理商: MC68HCL05J1ADW
Resets
Reset Types
MC68HC05J1A — Rev. 3.0
Technical Data
Resets
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at logic
0 at the end of 4064 tCYC, the MCU remains in the reset condition until
the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
A logic 0 applied to the RESET pin for one and one-half tCYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
5.3.3 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. See 8.4 COP
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0. The COP register,
shown in Figure 5-2, is a write-only register that returns the contents of
a ROM location when read.
The COP watchdog function is a mask option.
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU.
Address:
$07F0
Bit 7
6
54321
Bit 0
Read:
Write:
COPC
Reset:
UUUUUUU
0
= Unimplemented
U = Unaffected by reset
Figure 5-2. COP Register (COPR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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