參數(shù)資料
型號： MC68HCL05P1ADWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 57/124頁
文件大?。?/td> 623K
代理商： MC68HCL05P1ADWR2
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts
General Release Specification
MC68HC05P1A — Rev. 3.0
38
Interrupts
MOTOROLA
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked by the I bit
being clear in the condition code register (CCR) and the corresponding
interrupt enable bit being set, the processor proceeds with interrupt
processing. Otherwise, the next instruction is fetched and executed. The
SWI is executed the same as any other instruction, regardless of the
state of the I bit.
When an interrupt is processed, the CPU puts the register contents on
the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF0–$1FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in
Table 4-1, will be serviced first.
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was executed when the interrupt took place. Figure 4-1
shows the event sequence that occurs during interrupt processing.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
Enable
Bit
Interrupt
CPU
Interrupt
Vector
Address
N/A
Reset
RESET
$1FFE–$1FFF
N/A
Software
SWI
$1FFC–$1FFD
N/A
External Interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
ICIE
Timer Input
Capture
TIMER
$1FF8–$1FF9
TSR
OCF
OCIE
Timer Output
Compare
TIMER
$1FF8–$1FF9
TSR
TOF
TOIE
Timer Overow
TIMER
$1FF8–$1FF9
N/A
Unimplemented
N/A
$1FF6-$1FF7
N/A
Unimplemented
N/A
$1FF4-$1FF5
N/A
Unimplemented
N/A
$1FF2-$1FF3
N/A
Unimplemented
N/A
$1FF0-$1FF1
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