參數(shù)資料
型號(hào)： MC68HCP11A1VFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 84/158頁
文件大小： 776K
代理商： MC68HCP11A1VFN2
MOTOROLA
9-4
RESETS, INTERRUPTS, AND LOW POWER MODES
MC68HC11A8
TECHNICAL DATA
9
9.1.2.5 Real-Time Interrupt
The real time interrupt flag is cleared and automatic hardware interrupts are masked.
The rate control bits are cleared after reset and may be initialized by software before
the real time interrupt system is used.
9.1.2.6 Pulse Accumulator
The pulse accumulator system is disabled at reset so that the PAI input pin defaults to
being a general purpose input pin.
9.1.2.7 COP
The COP watchdog system is enabled if the NOCOP control bit in the system config-
uration control register (EEPROM cell) is clear, and disabled if NOCOP is set. The
COP rate is set for the shortest duration timeout.
9.1.2.8 SCI Serial l/O
The reset condition of the SCI system is independent of the operating mode. At reset,
the SCI baud rate is indeterminate and must be established by a software write to the
BAUD register. All transmit and receive interrupts are masked and both the transmitter
and receiver are disabled so the port pins default to being general purpose l/O lines.
The SCI frame format is initialized to an 8-bit character size. The send break and re-
ceiver wake up functions are disabled. The TDRE and TC status bits in the SCI status
register are both set, indicating that there is no transmit data in either the transmit data
register or the transmit serial shift register. The RDRF, IDLE, OR, NF, and FE receive-
related status bits are all cleared.
Note that upon reset in special bootstrap mode execution begins in the 192 byte boot
ROM. This firmware sets port D to wire-OR mode, establishes a baud rate, and en-
ables the SCI receiver and transmitter.
9.1.2.9 SPI Serial l/O
The SPI system is disabled by reset. The port pins associated with this function default
to being general purpose l/O lines.
9.1.2.10 A/D Converter
The A/D converter system configuration is indeterminate after reset. The conversion
complete flag is cleared by reset. The ADPU bit is cleared by reset thus disabling the
A/D system.
9.1.2.11 System
The EEPROM programming controls are all disabled so the memory system is config-
ured for normal read operation. The highest priority I interrupt defaults to being the ex-
ternal IRQ pin by PSEL[3:0] equal to 0:1:0:1. The IRQ interrupt pin is configured for
level sensitive operation (for wire-OR systems). The RBOOT, SMOD, and MDA bits in
the HPRIO register reflect the status of the MODB and MODA inputs at the rising edge
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