- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11942 > MC68HCP11E1VFNE2 (Freescale Semiconductor)IC MCU 8BIT 52-PLCC PDF資料下載
參數(shù)資料
| 型號： | MC68HCP11E1VFNE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 12/242頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 標(biāo)準包裝： | 23 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 2MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器類型： | ROMless |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁
SCI Error Detection
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
109
7.5.2 Address-Mark Wakeup
The serial characters in this type of wakeup consist of seven (eight if M = 1) information bits and an MSB,
which indicates an address character (when set to 1, or mark). The first character of each message is an
addressing character (MSB = 1). All receivers in the system evaluate this character to determine if the
remainder of the message is directed toward this particular receiver. As soon as a receiver determines
that a message is not intended for it, the receiver activates the RWU function by using a software write to
set the RWU bit. Because setting RWU inhibits receiver-related flags, there is no further software
overhead for the rest of this message.
When the next message begins, its first character has its MSB set, which automatically clears the RWU
bit and enables normal character reception. The first character whose MSB is set is also the first character
to be received after wakeup because RWU gets cleared before the stop bit for that frame is serially
received. This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method,
but there is a loss of efficiency because of the extra bit time for each character (address bit) required for
all characters.
7.6 SCI Error Detection
Three error conditions – SCDR overrun, received bit noise, and framing – can occur during generation of
SCI system interrupts. Three bits (OR, NF, and FE) in the serial communications status register (SCSR)
indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from the receive shift
register to the SCDR and the SCDR is already full (RDRF bit is set). When an overrun error occurs, the
data that caused the overrun is lost and the data that was already in SCDR is not disturbed. The OR is
cleared when the SCSR is read (with OR set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits.
The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with FE
equal to 1) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is set at
the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor
only recognizes the overrun error. The framing error flag inhibits further transfer of data into the SCDR
until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of
the SCDR.
7.7 SCI Registers
Five addressable registers are associated with the SCI:
Four control and status registers:
–
Serial communications control register 1 (SCCR1)
–
Serial communications control register 2 (SCCR2)
–
Baud rate register (BAUD)
–
Serial communications status register (SCSR)
One data register:
–
Serial communications data register (SCDR)
The SCI registers are the same for all M68HC11 E-series devices with one exception. The SCI system
for MC68HC(7)11E20 contains an extra bit in the BAUD register that provides a greater selection of baud
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 1828073-2 | ADPT ASSY, FLANGED, YELLOW |
| MC68HCP11E1CFNE2 | IC MCU 8BIT 52-PLCC |
| 1828073-1 | ADPT ASSY, FLANGED, RED |
| MC68711D3CFBE2 | IC MCU 8BIT 44-QFP |
| VE-B11-CU-F4 | CONVERTER MOD DC/DC 12V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HLC908JK3CP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QT1CFQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QT4CDW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QT4CFQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QY1CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/O ADC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。