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參數(shù)資料
| 型號(hào)： | MC68HLC908QY2CDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 40/186頁(yè) |
| 文件大?。?/td> | 2765K |
| 代理商： | MC68HLC908QY2CDT |
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Timer Interface Module (TIM)
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
134
Timer Interface Module (TIM)
MOTOROLA
period. Writing a larger value in an output compare interrupt routine (at the
end of the current pulse) could cause two output compares to occur in the
same counter overflow period.
14.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked pair
alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The output compare value in the TIM channel 0 registers
initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers
enables the TIM channel 1 registers to synchronously control the output after the
TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available
as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to
the currently active channel registers. User software should track the currently
active channel to prevent writing a new value to the active channel. Writing to the
active channel registers is the same as generating unbuffered output compares.
14.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM
can generate a PWM signal. The value in the TIM counter modulo registers
determines the period of the PWM signal. The channel pin toggles when the
counter reaches the value in the TIM counter modulo registers. The time between
overflows is the period of the PWM signal.
As Figure 14-4 shows, the output compare value in the TIM channel registers
determines the pulse width of the PWM signal. The time between overflow and
output compare is the pulse width. Program the TIM to clear the channel pin on
output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program the
TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1).
The value in the TIM counter modulo registers and the selected prescaler output
determines the frequency of the PWM output. The frequency of an 8-bit PWM
signal is variable in 256 increments. Writing $00FF (255) to the TIM counter
modulo registers produces a PWM period of 256 times the internal bus clock period
if the prescaler select value is 000. See 14.9.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the PWM
output. The pulse width of an 8-bit PWM signal is variable in 256 increments.
Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256
or 50%.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HLC908QY2CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/ADC - Bulk |
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