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| 型號： | MC68HRC05J5ADWR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 31/106頁 |
| 文件大小： | 1069K |
| 代理商： | MC68HRC05J5ADWR2 |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
INTERRUPTS
MC68HC05J5A
4-4
REV 2.1
The IRQ pin is a source of IRQ interrupts and a mask option can also enable the
other four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.
The last source of IRQ interrupt comes from PA7 whenever there is a falling edge
on PA7 and IRQE1 is enabled. There is no mask option associated with PA7 inter-
rupt.
Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes
from IRQ and IRQ1 latches. The IRQ latch will be set on the falling edge of the
IRQ pin or on any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled.
The IRQ1 latch will be set on the falling edge of PA7 if PA7 interrupt has been
enabled. If "edge-only" sensitivity is chosen by a mask option, only the IRQ latch
output can activate an IRQF ag which creates a request to the CPU to generate
the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following
cases:
1.
Falling edge on the IRQ pin.
2.
Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the rising edge signal on the clock input of the IRQ
latch can also activate an IRQF ag which creates an IRQ request to the CPU to
generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to
the following cases:
1.
Low level on the IRQ pin.
2.
Falling edge on the IRQ pin.
3.
High level on any PA0- PA3 pin with IRQ enabled (via mask option).
4.
Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).
The IRQE enable bit controls whether an active IRQF ag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specied by the contents of $0FFA and $0FFB.
The IRQ latch is automatically cleared by entering the interrupt service routine IF
IRQE1 enable bit is cleared. If IRQE1 enable bit is also set, the only way of clear-
ing IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one
to the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF ag,
regardless of the status of the IRQE1 bit, besides IRQ vector fetch. This condi-
tional reset of IRQF ag provides a way for the user to differentiate the interrupt
sources from IRQ and IRQ1 latches and also to make it J1A compatible if PA7
interrupt is not used. As long as the output state of the IRQF ag bit is active the
CPU will continuously re-enter the IRQ interrupt sequence until the active state is
removed or the IRQE enable bit is cleared.
PA7 interrupt source, if enabled by IRQE1 enable bit, triggers IRQ interrupt on
PA7 falling edge only. The IRQ1 latch (IRQF1 ag) can ONLY be cleared by writing
a logic one to the IRQR1 acknowledge bit in the ICSR. IRQ vector fetch can NOT
clear IRQF1 ag. IRQ interrupt caused by PA7 falling edge also vectors to $0FFA
and $0FFB.
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