參數(shù)資料
型號(hào)： MC68HRC705J5ACDWR3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 57/106頁
文件大小： 1069K
代理商： MC68HRC705J5ACDWR3
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05J5A
8-2
REV 2.1
8.1
OVERVIEW
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by
four. NTF1 has the same phase and frequency as the processor bus clock, PH2,
but is not stopped by the WAIT or HALT Modes. This signal drives an 8-bit ripple
counter. The value of this 8-bit ripple counter can be read by the CPU at any time
by accessing the Timer Counter Register (TCR) at address $09. A timer overow
function is implemented on the last stage of this counter, giving a possible inter-
rupt at the rate of fop/1024. The POR function is generated at fop/224 stage or at
fop/4064 stage, which is selected by a mask option.
The last stage of the 8-bit counter also drives a further 7-bit counter. The nal four
stages is used by the RTI circuit, giving possible RTI rates of fOP/2
14, f
OP /2
15,
fOP/2
16 or f
OP /2
17, selected by RT1 and RT0 (see Table 8-1). The RTI rate selec-
tor bits, and the RTI and TOF enable bits and ags are located in the Timer Con-
trol and Status Register at location $08.
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 224 or 4064 cycles, the power-on reset circuit is released which
again clears the counter chain and allows the device to come out of reset. At this
point, if RESET is not asserted, the timer will start counting up from zero and nor-
mal device operation will begin. If RESET is asserted at any time during operation
the counter chain will be cleared.
8.2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
The COP Watchdog is enabled by a mask option.
The COP Watchdog Timer function is implemented by using the output of the RTI
circuit and further dividing it by eight. The minimum COP reset rates are listed in
Table 8-1. If the COP circuit times out, an internal reset is generated and the nor-
mal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit-0 of address $0FF0.
When the COP is cleared, only the nal divide by eight stage (output of the RTI) is
cleared.
Figure 8-2. COP Watchdog Timer Location
8.3
MFT REGISTERS
The 15-stage Multi-function Timer contains two registers: a Timer Counter Regis-
ter and a Timer Control/Status Register.
7
W
R
6543210
COP
$0FF0
COPR
Reading $0FF0 returns the contents of Test ROM.
Unimplemented
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