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參數(shù)資料
| 型號(hào)： | MC68HRC98JL3EMFA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 152/180頁(yè) |
| 文件大?。?/td> | 2412K |
| 代理商： | MC68HRC98JL3EMFA |
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Functional Description
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
73
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
1.
If IRQ = VTST:
–
Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)
–PTB3 = low
2.
If IRQ = VTST:
–
Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)
–
PTB3 = high
3.
If $FFFE & $FFFF is blank (contains $FF):
–
Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)
–IRQ = VDD
If VTST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VTST applied to IRQ upon
monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to
OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT frequency is equal to the
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Table 7-1. Monitor Mode Entry Requirements and Options
IRQ
$FFFE
and
$FFFF
PTB3
(1
)
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VTST for monitor mode entry.
The OSC1 clock must be 50% duty cycle for this condition.
PTB2
PTB1
PTB0
OSC1 Frequency
Bus
Frequency
Comments
VTST
(2)
X
0011
4.9152MHz
2.4576MHz
(OSC1 ÷ 2)
High-voltage entry to monitor
mode.(3)
9600 baud communication on
PTB0. COP disabled.
3. For IRQ = VTST:
MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
VTST
X
1011
9.8304MHz
2.4576MHz
(OSC1 ÷ 4)
VDD
BLANK
(contain
$FF)
XXX
1
9.8304MHz
2.4576MHz
(OSC1 ÷ 4)
Low-voltage entry to monitor
mode.(4)
9600 baud communication on
PTB0. COP disabled.
4. For IRQ = VDD:
MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
VDD
NOT
BLANK
XXXX
At desired
frequency
OSC1 ÷ 4
Enters User mode.
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