參數(shù)資料
型號(hào): MC68HSC05C12ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 111/156頁
文件大?。?/td> 756K
代理商: MC68HSC05C12ACFN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Timer
General Release Specification
MC68HC05C12A Rev. 3.0
58
Timer
MOTOROLA
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-
running counter transfer, since they occur on opposite edges of the
internal bus clock. Figure 8-3 shows the logic of the input capture
function.
Figure 8-3. Input Capture Operation
8.6 Timer Control Register
The TCR is a read/write register containing five control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
INPUT CAPTURE REGISTER HIGH
INPUT CAPTURE REGISTER LOW
TIMER REGISTER HIGH
TCMP
EDGE
SELECT/DETECT
LOGIC
TIMER
INTERRUPT
REQUEST
TIMER REGISTER LOW
15
0
15
8 7
0
TIMER STATUS REGISTER
$0013
TIMER CONTROL REGISTER
$0012
ICIE
OCIE
T
OIE
ICF
OCF
TO
F
87
$0018
$0019
$0014
$0015
IEDG
LATCH
Address:
$12
Bit 7
654321
Bit 0
Read:
ICIE
OCIE
TOIE
0
IEDG
OLVL
Write:
Reset:
000000
U
0
U = Unaffected
Figure 8-4. Timer Control Register (TCR)
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