參數(shù)資料
Interrupts
Hardware Interrupts
MC68HC05P1A Rev. 3.0
General Release Specification
MOTOROLA
Interrupts
43
NON-DISCLOSURE
AGREEMENT
REQUIRED
be enabled. The interrupt service routine address is specified by the
contents of memory locations $1FF8 and $1FF9.
4.5.4 Output Compare Interrupt
The output compare interrupt is generated by the 16-bit timer as
described in Section 8. 16-Bit Timer. The output compare interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address
is specified by the contents of memory locations $1FF8 and $1FF9.
4.5.5 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 8. 16-Bit Timer. The timer overflow interrupt flag is located in
register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear for the timer overflow interrupt
to be enabled. This internal interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
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