Serial Communications Interface (SCI)
SCI Operation
MC68HC705C8A
—
Rev. 3
Technical Data
MOTOROLA
Serial Communications Interface (SCI)
125
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and
then writing data to the SCDR begins the transmission. At the start
of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of logic 1s. After the
preamble shifts out, the control logic transfers the SCDR data into
the shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the shift register, and a logic 1 stop
bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$000D
Baud Rate Register
(Baud)
See page 136.
Read:
SCP1
SCP0
SCR2
SCR1
SCR0
Write:
Reset:
U
U
0
0
U
U
U
U
$000E
SCI Control Register 1
(SCCR1)
See page 130.
Read:
R8
T8
M
WAKE
Write:
Reset:
U
U
U
U
$000F
SCI Control Register 2
(SCCR2)
See page 131.
Read:
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Write:
Reset:
0
0
0
0
0
0
0
0
$0010
SCI Status Register
(SCSR)
See page 133.
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
Write:
Reset:
1
1
0
0
0
0
0
U
$0011
SCI Data Register
(SCDR)
See page 129.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
U = Unaffected
Figure 10-3. SCI Transmitter I/O Register Summary