參數(shù)資料
型號: MC68L11D0CFBE2R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 2 MM HEIGHT, 0.80 MM PITCH, QFP-44
文件頁數(shù): 105/131頁
文件大?。?/td> 1640K
代理商: MC68L11D0CFBE2R
MC68HC11D3
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
7-9
The prescale bits, SCP[1:0], determine the highest baud rate and the SCR[2:0] bits se-
lect an additional binary submultiple (
≥1, ≥2, ≥4, through ≥128) of this highest baud
rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3 illustrates the SCI baud rate timing chain. The prescale select bits deter-
mine the highest baud rate. The rate select bits determine additional divide by two
stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result
of dividing the RT clock by 16.
Table 7-2 Baud Rate Selects
SCR[2:0]
Divide
Prescaler
Highest Baud Rate
(Prescaler Output from Previous Table)
By
4800
9600
38.4 K
0 0 0
1
4800
9600
38.4 K
0 0 1
2
2400
4800
19.2 K
0 1 0
4
1200
2400
9600
0 1 1
8
600
1200
4800
1 0 0
16
300
600
2400
1 0 1
32
150
300
1200
1 1 0
64
150
600
1 1 1
128
300
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