參數(shù)資料
型號： MC68L11K3FN1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 32/80頁
文件大?。?/td> 420K
代理商： MC68L11K3FN1
MOTOROLA
32
M68HC11 K Series
MC68HC11KTS/D
4.3.3 General-Purpose Chip Selects (CSGP1, CSGP2)
The general-purpose chip selects are the most flexible and programmable and have the most control
bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable.
Clock stretching can be set from zero to three cycles. Each chip select can be programmed to become
active whenever the CPU address enters a memory expansion window regardless of the actual bank
selected. This is known as following a window.
Each general purpose chip select can be configured to drive the program chip select. CSGP1 can be
configured to drive CSGP2 or the program chip select. Using one chip select to drive another allows the
same device to cover the address space defined by both chip selects. The two chip selects are con-
nected to an internal OR gate. The output of the OR gate is then driven onto the pin corresponding to
the driven chip select. For example, this is useful when the same external device is used with both bank
windows but the windows are opened independently. In cases where one chip select drives another,
determine the priority from the following table.
4.3.4 Chip Select Priorities
To minimize chip select conflicts (with one another or with internal memory and registers), the priority
is determined by the GCSPR bit in the CSCTL register. Refer to the following table.
4.3.5 Chip Select Control Registers
There are six chip select control registers. Chip select functions are enabled by control bits in CSCTL
register. Chip selects are configured by bits in CSCSTR, IOEN, IOPL, IOCSA, and IOSZ registers.
IOEN —I/O Chip Select Enable
0 = CSIO disabled
1 = CSIO enabled
IOPL —I/O Chip Select Polarity Select
0 = CSIO active low
1 = CSIO active high
Condition
Priority
GPCS1
GPCS1
GPCS2
GPCS1
GPCS1 drives GPCS2
GPCS1 drives PCS
GPCS2 drives PCS
GPCS1 and GPCS2 drive PCS
GCSPR = 0
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
Program Chip Select
GP Chip Select 1
GP Chip Select 2
GCSPR = 1
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
GP Chip Select 1
GP Chip Select 2
Program Chip Select
CSCTL
—
Chip Select Control
$005B
Bit 7
IOEN
0
6
5
4
3
2
1
Bit 0
PCSZB
0
IOPL
0
IOCSA
0
IOSZ
0
GCSPR
0
PCSEN
1
PCSZA
0
RESET:
相關(guān)PDF資料
PDF描述
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