Table of Contents
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vi
MC68LC302 REFERENCE MANUAL
MOTOROLA
2.4.4.1.4
SLOW_GO Mode...................................................................................2-14
2.4.4.1.5
NORMAL Mode......................................................................................2-14
2.4.4.1.6
IMP Operation Mode Control Register (IOMCR) ...................................2-14
2.4.4.1.7
Low Power Drive Control Register (LPDCR) .........................................2-15
2.4.4.1.8
IMP Power Down Register (IPWRD) .....................................................2-15
2.4.4.1.9
Default Operation Modes. ......................................................................2-15
2.4.4.2
Low Power Support................................................................................2-15
2.4.4.2.1
Enter the SLOW_GO mode ...................................................................2-15
2.4.4.2.2
Entering the STOP/ DOZE/ STAND_BY Mode......................................2-16
2.4.4.2.3
IMP Wake-Up from Low Power STOP Modes .......................................2-17
2.4.4.2.4
IMP Wake-Up Control Register (IWUCR) ..............................................2-17
2.4.4.3
Fast Wake-Up ........................................................................................2-18
2.4.4.3.5
Ring Oscillator Control Register (RINGOCR) ........................................2-19
2.4.4.3.6
Ring Oscillator Event Register (RINGOEVR). .......................................2-20
2.5
MC68LC302 Dual Port RAM..................................................................2-20
2.6
Internal Registers map...........................................................................2-23
Section 3
System Integration Block (SIB)
3.1
System Control ........................................................................................3-1
3.1.1
System Control Register (SCR) ...............................................................3-2
3.1.2
System Status Bits...................................................................................3-3
3.1.3
System Control Bits .................................................................................3-3
3.1.4
Freeze Control .........................................................................................3-5
3.1.5
Hardware Watchdog ................................................................................3-5
3.2
Programmable Data Bus Size Switch ......................................................3-6
3.2.1
Bus Switch Register (BSR) ......................................................................3-6
3.2.2
Basic Procedure:......................................................................................3-6
3.3
Load Boot Code from An SCC.................................................................3-7
3.4
DMA Control ..........................................................................................3-10
3.4.1
MC68LC302 Differences........................................................................3-10
3.4.2
IDMA Registers (Independent DMA Controller).....................................3-11
3.4.2.1
Channel Mode Register (CMR)..............................................................3-11
3.4.2.2
Source Address Pointer Register (SAPR) .............................................3-13
3.4.2.3
Destination Address Pointer Register (DAPR).......................................3-13
3.4.2.4
Function Code Register (FCR) ..............................................................3-13
3.4.2.5
Byte Count Register (BCR)....................................................................3-13
3.4.2.6
Channel Status Register (CSR) .............................................................3-13
3.5
Interrupt Controller .................................................................................3-14
3.5.1
Interrupt Controller Key Differences.......................................................3-14
3.5.2
Interrupt Controller Programming Model................................................3-14
3.5.2.1
Global Interrupt Mode Register (GIMR) .................................................3-14
3.5.2.2
Interrupt Pending Register (IPR)............................................................3-15
3.5.2.3
Interrupt Mask Register (IMR)................................................................3-16
3.5.2.4
Interrupt In-Service Register (ISR).........................................................3-16