參數(shù)資料
型號： MC68MH360CZQ25L
廠商： Freescale Semiconductor
文件頁數(shù)： 72/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
System interface
— On-chip bus arbitration for serial DMAs with no performance penalty
— Efcient bus usage (no bus usage for nonactive channels and active channels that
have nothing to transmit)
— Efcient control of the interrupts to the CPU
— Supports external buffer descriptors table
— Uses on-chip enlarged dual-ported RAM for parameter storage
1.4 The Time Slot Assigner and the QMC
The time slot assigner (TSA) in the MH devices is no different from the other versions. This
section discusses the new possibilities when using the TSA in combination with the QMC.
The QMC protocol can be executed in nonmultiplexed serial interface (NMSI) mode, but
the usual operating mode takes advantage of the programmable time slot assigner,.
A frame synchronization pulse alerts the time slot assigner to start counting clock pulses.
The user programs what bits are routed to the different internal serial channels. The TSA is
an intelligent multiplexer that restarts its sequence on every frame synchronization pulse.
External strobe signals allow other devices that do not have built-in time slot assigner
functions to participate in the TDM interface. This is very useful when interfacing to the
MC68302 or other telecommunication devices like codecs.
The time slot assigner is not limited to standard TDM lines. It is a exible, programmable
device that allows the user to route any combination of bits and bytes to any channel. For
example, the user can transmit 3 bits from SCC2, skip 12 bytes, and then transmit another
17 bits from SCC1. This routing must be programmed into the TSA memory. The
complexity of the routing is limited only by the number of program entries in the TSA.
Ideal for TDM bridging applications, the MC68MH360 and MPC860MH have two
independent time slot assigners and physical interfaces. A complete set of independent
receive and transmit clock signals, as well as independent synchronization signals, are
available for each TDM.
1.5 The Serial Interface (SI)
Functions such as frame synchronization, loopback, echo, and inverted signals are
performed in the serial interface and cannot be achieved in NMSI mode. It is recommended
to use the serial interface even if only one SCC is used for the TDM bus.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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