參數(shù)資料
型號: MC705J1ACDWE
廠商: Freescale Semiconductor
文件頁數(shù): 137/162頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 1.2K RAM 20-SOIC
標準包裝: 38
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Resets and Interrupts
Resets and Interrupts
4.4.3 Timer Interrupts
The timer can generate these interrupt requests:
Real time
Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
4.4.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
4.4.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
4.4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
Stores the CPU registers on the stack in the order shown in
Sets the I bit in the condition code register to prevent further
interrupts
Loads the program counter with the contents of the appropriate
interrupt vector locations:
$07FC and $07FD (software interrupt vector)
$07FA and $07FB (external interrupt vector)
$07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-6.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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