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| 型號(hào)： | MC705P6AMDWE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 39/98頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 4.6K OTP 2.1MHZ 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 2.1MHz |
| 連通性： | SIO |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 21 |
| 程序存儲(chǔ)器容量： | 4.5KB（4.5K x 8） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 176 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
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Serial Input/Output Port (SIOP)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
44
Freescale Semiconductor
7.3.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits. Figure 7-4 shows the position of each bit
in the register and indicates the value of each bit after reset.
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer
has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If the SPIF is cleared before the
last rising edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of
the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL
bit will be set again. Reset clears the DCOL bit.
7.3.3 SIOP Data Register (SDR)
This register is located at address $000C and serves as both the transmit and receive data register.
Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will destroy the previous contents. The
SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be
transmitted and/or received. Figure 7-5 shows the position of each bit in the register. This register is not
affected by reset.
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00000000
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
Address:
$000C
Bit 7
654321
Bit 0
Read:
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Write:
Reset:
Unaffected by reset
Figure 7-5. Serial Port Data Register (SDR)
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