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| 型號： | MC7447AVS1000NB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 1000MHZ 360-FCCLGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應商設備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
14
Freescale Semiconductor
Electrical and Thermal Characteristics
5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7447A. After fabrication, functional
parts are sorted by maximum processor core frequency as shown in Section 5.2.1, “Clock AC
Specifications,” and tested for conformance to the AC specifications for that frequency. The processor core
frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals,
and can be dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum
processor core frequency; see Section 11, “Ordering Information,” for information on ordering parts. DFS
is described in Section 9.8.5, “Dynamic Frequency Switching (DFS).”
5.2.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested
operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8, is
considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK
frequency for any application of the MPC7447A will be a function of the AC timings of the MPC7447A,
the AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so
forth, and may be less than the value given in Table 8.
NOTE
The core frequency information in this table applies when operating the
device at the nominal core voltage indicated in Table 4. For core frequency
specifications at derated core voltage conditions, see Section 5.3, “Voltage
Typical
4.1
4.0
3.2
4.0
W
1, 2
Notes:
1. These values specify the power consumption for the core power supply (VDD) at nominal voltage and apply
to all valid processor bus frequencies and configurations. The values do not include I/O supply power (OVDD)
or PLL supply power (AVDD). OVDD power is system dependent but is typically < 5% of VDD power. Worst
case power consumption for AVDD < 3 mW.
2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while
running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see
Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the
execution units maximally busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep
mode. As a result, power consumption for this mode is not tested.
5. Power consumption for these devices is artificially constrained during screening to assure lower power
consumption than other speed grades.
Table 7. Power Consumption for MPC7447A (continued)
Processor (CPU) Frequency
Unit
Notes
1000
1267
1333 5
1420 MHz
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