參數(shù)資料
型號： MC7447AVU1000LB
廠商： Freescale Semiconductor
文件頁數(shù)： 34/56頁
文件大小： 0K
描述： IC MPU RISC 32BIT 360-BGA
標準包裝： 44
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 1.0GHz
電壓： 1.3V
安裝類型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應商設備封裝： 360-FCCBGA（25x25）
包裝： 托盤
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
4
Freescale Semiconductor
Features
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm).
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle
throughput
– 4-cycle FPR load latency (single, double) with 1-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch. (This includes instructions that
are assigned a space in the CQ but not in an issue queue.)
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
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