參數(shù)資料
型號(hào)： MC7447AVU600NB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 16/56頁(yè)
文件大小： 0K
描述： IC MPU RISC 32BIT 360-BGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 600MHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
23
Pinout Listings
7
Pinout Listings
Table 12 provides the pinout listing for the MPC7447A, 360 HCTE package. The pinouts of the
MPC7447A and MPC7447 are pin compatible, but there have been some changes. An MPC7447A may
be populated on a board designed for a MPC7447 provided all pins defined as ‘no connect’ for the
MPC7447 are unterminated as required by the MPC7457 RISC Microprocessor Hardware Specifications.
The MPC7447A uses pins previously marked ‘no connect’ for the temperature diode pins and for
additional power and ground connections. Because these ‘no connect’ pins in the MPC7447 360 pin
package are not driven in functional mode, an MPC7447 can be populated in an MPC7447A board. See
Section 9.4, “Connection Recommendations,” for additional information.
NOTE
Caution must be exercised when performing boundary scan test operations
on a board designed for an MPC7447A but populated with an MPC7447.
This is because in the MPC7447 it is possible to drive the latches associated
with the former ‘no connect’ pins in the MPC7447, potentially causing
contention on those pins. To prevent this, ensure that these pins are not
connected on the board or, if they are connected, ensure that the states of
internal MPC7447 latches do not cause these pins to be driven during board
testing.
NOTE
This pinout is not compatible with the MPC750, MPC7400, or MPC7410
360 BGA and LGA package.
Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package
Signal Name
Pin Number
Active
I/O
I/F Select1
Notes
A[0:35]
E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12,
L3, G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5,
P5, N3, T1, V2, U1, N5, W1, B12, C4, G10, B11
High
I/O
BVSEL
2
AACK
R1
Low
Input
BVSEL
AP[0:4]
C1, E3, H6, F5, G7
High
I/O
BVSEL
2
ARTRY
N2
Low
I/O
BVSEL
3
AVDD
A8
—
Input
N/A
BG
M1
Low
Input
BVSEL
BMODE0
G9
Low
Input
BVSEL
4
BMODE1
F8
Low
Input
BVSEL
5
BR
D2
Low
Output
BVSEL
B7
High
Input
BVSEL
1, 6
CI
J1
Low
Output
BVSEL
CKSTP_IN
A3
Low
Input
BVSEL
CKSTP_OUT
B1
Low
Output
BVSEL
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