
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7448 as defined in
Figure 4 and
Table 9. Processor Bus AC Timing Specifications1
At recommended operating conditions. See
Table 4.Parameter
Symbol 2
All Speed Grades
Unit
Notes
Min
Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1]
tAVKH
tDVKH
tIVKH
tMVKH
1.5
—
ns
—
8
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1]
tAXKH
tDXKH
tIXKH
tMXKH
0
—
ns
—
8
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
tKHAV
tKHDV
tKHOV
tKHTSV
tKHARV
—
1.8
ns
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
tKHAX
tKHDX
tKHOX
tKHTSX
tKHARX
0.5
—
ns
SYSCLK to output enable
tKHOE
0.5
—
ns
5
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL