參數(shù)資料
型號: MC7448VU600NC
廠商: Freescale Semiconductor
文件頁數(shù): 39/60頁
文件大?。?/td> 0K
描述: IC MPU RISC 32BIT 360-FCCBGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 600MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 360-CBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 360-FCCBGA(25x25)
包裝: 托盤
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
44
Freescale Semiconductor
System Design Information
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 21 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-
Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. Although Freescale recommends that the COP header be designed into the system as shown in
Figure 21, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 21 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 21; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 21 is common to all known emulators.
The QACK signal shown in Figure 21 is usually connected to the bridge chip or other system control logic
in a system and is an input to the MPC7448 informing it that it can go into the quiescent state. Under
normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7448
must see this signal asserted (pulled down). While shown on the COP header, not all emulator products
drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal.
Additionally, some emulator products implement open-drain type outputs and can only drive QACK
asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is
not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down
operation, QACK should be merged through logic so that it also can be driven by the bridge or system
logic.
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