參數(shù)資料
型號(hào)： MC7457VG733NC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 8/71頁(yè)
文件大?。?/td> 0K
描述： IC MPU RISC 733MHZ 483FCCBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC74xx
處理器類(lèi)型： 32-位 MPC74xx PowerPC
速度： 733MHz
電壓： 1.1V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 483-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 483-FCCBGA（29x29）
包裝： 托盤(pán)
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Electrical and Thermal Characteristics
Freescale Semiconductor
16
Table 7 provides the power consumption for the MPC7457.
Capacitance,
Vin = 0 V, f = 1 MHz
L3 interface
—
Cin
—9.5
pF
5
All other inputs
—
8.0
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction
(for example, both OVDD and VDD vary by either +5% or –5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. Applicable to L3 bus interface only.
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
Full-Power Mode
Typical
14.8
15.8
17.5
18.3
W
1, 2
Maximum
21.0
22.0
24.2
25.6
W
1, 3
Nap Mode
Typical
5.2
W
1, 2
Sleep Mode
Typical
5.1
W
1, 2
Deep Sleep Mode (PLL Disabled)
Typical
5.0
W
1, 2
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and
GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD power. Worst
case power consumption for AVDD < 3 mW.
2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while running the
Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 4) while
running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a
result, power consumption for this mode is not tested.
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic
Nominal
Bus
Voltage 1
Symbol
Min
Max
Unit
Notes
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