<thead id="45pmn"><delect id="45pmn"><fieldset id="45pmn"></fieldset></delect></thead>
  • <dfn id="45pmn"></dfn>
  • 參數(shù)資料
    型號(hào): MC74AC109
    廠商: ON SEMICONDUCTOR
    英文描述: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
    中文描述: 雙JK上升沿觸發(fā)器
    文件頁(yè)數(shù): 1/6頁(yè)
    文件大?。?/td> 197K
    代理商: MC74AC109
    5-1
    FACT DATA
    The MC74AC109/74ACT109 consists of two high-speed completely independent
    transition clocked JK flip-flops. The clocking operation is independent of rise and fall
    times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
    MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
    Asynchronous Inputs:
    LOW input to SD (Set) sets Q to HIGH level
    LOW input to CD (Clear) sets Q to LOW level
    Clear and Set are independent of clock
    Simultaneous LOW on CD and SD makes both Q and Q HIGH
    Outputs Source/Sink 24 mA
    ACT109 Has TTL Compatible Inputs
    15
    16
    14
    13
    12
    11
    10
    2
    J1
    1
    3
    4
    5
    6
    7
    VCC
    9
    8
    CD2
    J2
    K2
    CP2
    SD2
    Q2
    Q2
    CD1
    K1
    CP1
    SD1
    Q1
    Q1
    GND
    J1
    K1
    CP1
    SD1
    Q1
    Q1
    CD
    J
    K
    CP
    SD
    Q
    Q
    CD1
    PIN NAMES
    J1, J2, K1, K2
    CP1, CP2
    CD1, CD2
    SD1, SD2
    Q1, Q2, Q1, Q2
    Data Inputs
    Clock Pulse Inputs
    Direct Clear Inputs
    Direct Set Inputs
    Outputs
    TRUTH TABLE
    Inputs
    Outputs
    SD
    L
    H
    L
    H
    H
    H
    H
    H
    CD
    H
    L
    L
    H
    H
    H
    H
    H
    CP
    J
    K
    Q
    Q
    X
    X
    X
    X
    X
    X
    L
    H
    L
    H
    X
    X
    X
    X
    L
    L
    H
    H
    X
    H
    L
    H
    L
    L
    H
    H
    H
    Toggle
    Q0
    H
    Q0
    Q0-
    L
    Q0-
    L
    H = HIGH Voltage Level
    L = LOW Voltage Level
    = LOW-to-HIGH Clock Transition
    X = Immaterial
    Q0(Q0) = Previous Q0(Q0) before
    LOW-to-HIGH Transition of Clock
    DUAL JK POSITIVE
    EDGE-TRIGGERED
    FLIP-FLOP
    N SUFFIX
    CASE 648-08
    PLASTIC
    D SUFFIX
    CASE 751B-05
    PLASTIC
    LOGIC SYMBOL
    SD
    Q
    J
    CP
    Q
    CD
    K
    SD
    Q
    J
    CP
    Q
    CD
    K
    相關(guān)PDF資料
    PDF描述
    MC74ACT109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
    MC74AC109D DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
    MC74AC109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
    MC74ACT109N DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
    MC74ACT10D TRIPLE 3-INPUT NAND GATE
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    MC74AC109D 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop
    MC74AC109DR2 制造商:Motorola Inc 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SOP
    MC74AC109DT 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop
    MC74AC109DTR2 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop
    MC74AC109M 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop