參數(shù)資料
型號: MC74ACT74DTR2
廠商: ON Semiconductor
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL TYPE D 14TSSOP
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標準包裝: 2,500
系列: 74ACT
功能: 設置(預設)和復位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 210MHz
延遲時間 - 傳輸: 5.5ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2006
October, 2006 Rev. 7
1
Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
Dual DType Positive
EdgeTriggered FlipFlop
The MC74AC74/74ACT74 is a dual Dtype flipflop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
Outputs Source/Sink 24 mA
′ACT74 Has TTL Compatible Inputs
PbFree Packages are Available
CP1
CD2
CP2
13
14
12
11
10
9
8
2
1
34567
VCC
CD1
D1
CP1 SD1
Q1
CD2 D2
CP2 SD2
Q2
CD1
SD1
Q1
D1
SD2
Q2
D2
GND
Q1
Figure 1. Pinout: 14Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
FUNCTION
D1, D2
Data Inputs
CP1, CP2
Clock Pulse Inputs
CD1, CD2
Direct Clear Inputs
SD1, SD2
Direct Set Inputs
Q1, Q1, Q2,
Q2
Outputs
TSSOP14
DT SUFFIX
CASE 948G
1
14
SOEIAJ14
M SUFFIX
CASE 965
1
14
SOIC14
D SUFFIX
CASE 751A
1
14
1
14
PDIP14
N SUFFIX
CASE 646
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
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