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參數(shù)資料
| 型號(hào)： | MC74F323N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| 中文描述： | F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | 738-03 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 126K |
| 代理商： | MC74F323N |
4-151
FAST AND LS TTL DATA
MC74F323
FUNCTION TABLE
Inputs
SR
S1
X
H
L
H
L
S0
X
H
H
L
L
CP
↑
↑
↑
↑
X
Response
L
H
H
H
H
Synchronous Reset: Q0–Q7 = LOW
Parallel Load: I/On
o
Qn
Shift Right: DS0
o
Q0, Q0
o
Q1, etc.
Shift Left: DS7
o
Q7, Q7
o
Q6, etc.
Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH clock transition.
FUNCTIONAL DESCRIPTION
The MC74F323 contains eight edge-triggered D-type
flips-flops and the interstage logic necessary to perform
synchronous reset, shift left, shift right, parallel load and hold
operations. The type of operation is determined by S0 and S1,
as shown in the Function Table. All flip-flop outputs are
brought out through 3-state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All other
state changes are initiated by the LOW-to-HIGH CP transition.
Inputs can change when the clock is in either state provided
only that the recommended set-up and hold times, relative to
the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(Unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
VIL
VIK
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage
Input Clamp Diode Voltage
–1.2
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
Q0/Q7
74
2.5
V
IOH = –1.0 mA
VCC = 4.5 V
VCC = 4.75 V
VCC = 4.75 V
VCC = 4.5 V
74
2.7
I/O
74
2.7
3.4
V
IOH = –3.0 mA
74
2.4
VOL
Output LOW Voltage
Q0/Q7
I/O
0.5
V
IOL = 20 mA
IOL = 24 mA
VCC = MIN
0.5
IIH
Input HIGH Current
Q0/Q7
I/O
20
μ
A
VCC = MAX, VIN = 2.7 V
70
Q0/Q7
I/O
0.1
mA
VCC = MAX
VIN = 7.0 V
VIN = 5.5 V
1.0
IIL
Input LOW Current
S0, S1
Other Inputs
–1.2
mA
VCC = MAX, VIN = 0.5 V
–0.6
IOZH
Off-State Output Current,
High-Level Voltage Applied
70
μ
A
mA
VCC = MAX
VOUT = 2.7 V
VOUT = 5.5 V
1.0
IOZL
Off-State Output Current,
Low-Level Voltage Applied
–0.6
mA
VCC = MAX, VOUT = 0.5 V
IOS
ICC
NOTES:
1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
Output Short Circuit Current (Note 2)
–60
–150
mA
VCC = MAX
VOUT = 0 V
Outputs Disabled
Total Supply Current
95
mA
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