參數(shù)資料
型號: MC74HC03ADG
廠商: ON Semiconductor
文件頁數(shù): 1/8頁
文件大?。?/td> 0K
描述: IC GATE NAND QUAD 2INP 14-SOIC
標準包裝: 55
系列: 74HC
邏輯類型: 與非門
電路數(shù): 4
輸入數(shù): 2
特點: 開路漏極
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: -,5.2mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時的最大傳播延遲: 20ns @ 6V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應商設備封裝: 14-SOICN
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 1122 (CN2011-ZH PDF)
其它名稱: MC74HC03ADG-ND
MC74HC03ADGOS
Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 13
1
Publication Order Number:
MC74HC03A/D
MC74HC03A
Quad 2-Input NAND Gate
with Open-Drain Outputs
HighPerformance SiliconGate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a highperformance
MOS NChannel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wiredAND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.
Features
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
PIN 14 = VCC
PIN 7 = GND
* Denotes open-drain outputs
LOGIC DIAGRAM
3,6,8,11
Y*
1,4,9,12
A
2,5,10,13
B
OUTPUT
PROTECTION
DIODE
VCC
Pinout: 14Lead Packages (Top View)
13
14
12
11
10
9
8
2
1
34567
VCC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
http://onsemi.com
L
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
Z
L
Y
Z = High Impedance
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G
= PbFree Package
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOIC14
D SUFFIX
CASE 751A
14
1
HC03AG
AWLYWW
1
14
HC
03A
ALYWG
G
1
14
(Note: Microdot may be in either location)
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