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參數(shù)資料
型號(hào): MC74HC03ADR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC GATE NAND QUAD 2INPUT 14SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74HC
邏輯類(lèi)型: 與非門(mén)
電路數(shù): 4
輸入數(shù): 2
特點(diǎn): 開(kāi)路漏極
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: -,5.2mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 20ns @ 6V,50pF
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOICN
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MC74HC03ADR2OSDKR
MC74HC03A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
SOIC Package
TSSOP Package
500
450
mW
Tstg
Storage Temperature
–65 to + 150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
–55
+125
°C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
1000
500
400
ns
DESIGN GUIDE
Criteria
Value
Unit
Internal Gate Count*
7.0
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
Speed Power Product
0.0075
pJ
*Equivalent to a twoinput NAND gate
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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