參數(shù)資料
型號(hào): MC74HC132ADR2
廠商: ON SEMICONDUCTOR
元件分類(lèi): 通用總線功能
英文描述: Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
中文描述: HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: SOIC-14
文件頁(yè)數(shù): 2/6頁(yè)
文件大?。?/td> 189K
代理商: MC74HC132ADR2
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
Power Dissipation in Still Air,Plastic or Ceramic DIP
750
500
mW
Tstg
TL
Storage Temperature
SOIC Package
– 65 to + 150
C
Lead Temperature, 1 mm from Case for 10 Seconds
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
(Ceramic DIP)
300
(Referenced to GND)
TA
tr, tf
Operating Temperature, All Package Types
– 55
+ 125
C
Input Rise and Fall Time (Figure 1)
no
ns
V
Maximum Positive–Going
Input Threshold Voltage
|Iout|
20
A
2.0
4.5
1.5
3.15
1.5
3.15
1.5
3.15
Input Threshold Voltage
|Iout|
20
μ
A
4.5
2.3
2.25
2.25
V
(Figure 3)
6.0
2.6
2.65
2.65
VT– min
Minimum Negative–Going
Vout = VCC – 0.1 V
2.0
0.3
0.3
0.3
Note 2
Maximum Hysteresis Voltage
(Figure 3)
|Iout|
20
μ
A
2.0
4.5
1.2
2.25
1.2
2.25
1.2
2.25
V
Note 2
(Figure 3)
20
μ
A
4.5
0.4
0.4
0.4
V
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
相關(guān)PDF資料
PDF描述
MC74HC132AN Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
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