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參數(shù)資料
| 型號： | MC74HC133N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 13-Input NAND Gate |
| 中文描述： | HC/UH SERIES, 13-INPUT NAND GATE, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 146K |
| 代理商： | MC74HC133N |
MC74HC133
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
35
53
6.0
13
44
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
27
pF
tr
VCC
GND
90%
50%
10%
90%
50%
10%
ANY INPUT
OUTPUT Y
tPHL
tPLH
tTHL
tTLH
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
tf
1
2
3
4
5
6
7
10
12
13
14
15
9
Y
A
B
C
D
E
F
G
H
I
J
K
L
M
LOGIC DIAGRAM
11
Figure 1. Switching Waveforms
Figure 2. Test Circuit
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