參數(shù)資料
型號: MC74HC137
廠商: Motorola, Inc.
英文描述: 1-of-8 Decoder/Demultiplexer with Address Latch
中文描述: 1 - 8解碼器/解復(fù)用器的地址鎖存
文件頁數(shù): 4/6頁
文件大?。?/td> 210K
代理商: MC74HC137
MC74HC137
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is enabled,
determine which of the eight outputs is selected.
CONTROL INPUTS
CS1, CS2 (Pins 6, 5)
Chip–Select inputs. For CS1 at a high level and CS2 at a
low level, the chip is enabled and the outputs follow the ad-
dress inputs (Latch Enable = L). For any other combination of
CS1 and CS2, the outputs are at a high level.
Latch Enable (Pin 4)
Latch–Enable input. A high level at this input latches the
Address. A low level at this input allows the outputs to follow
the data at the Address pins (CS1 = H and CS2 = L).
OUTPUTS
Y0 – Y7
Active–low outputs. One of these eight outputs is selected
when the chip is enabled (CS1 = H and CS2 = L) and the
data on the A0, A1, and A2 inputs correspond to that par-
ticular output. The selected output is at a low level while all
others remain at a high level.
SWITCHING WAVEFORMS
Figure 1.
50%
tPHL
tPLH
tTHL
tTLH
VCC
GND
Figure 2.
Figure 3.
Figure 4.
Figure 5.
VALID
VALID
INPUT A
OUTPUT Y
50%
VCC
GND
tr
tf
tPHL
tPLH
OUTPUT Y
CS2
90%
50%
10%
90%
50%
10%
VCC
GND
tPHL
50%
tPLH
50%
50%
tw
OUTPUT Y
LATCH
ENABLE
tr
VCC
GND
tPLH
tTLH
90%
50%
10%
OUTPUT Y
CS1
tPHL
90%
50%
10%
tTHL
LATCH
ENABLE
VCC
GND
VCC
GND
50%
50%
VALID
tsu
th
INPUT A
* Includes all probe and jig capacitance
Figure 6. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
tf
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