參數(shù)資料
型號(hào): MC74HC164ADR2G
廠商: ON Semiconductor
文件頁數(shù): 8/11頁
文件大小: 0K
描述: IC SHIFT REGISTER 8BIT 14SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74HC
邏輯類型: 移位寄存器
輸出類型: 標(biāo)準(zhǔn)
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
功能: 串行至并行
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOICN
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MC74HC164ADR2GOSDKR
MC74HC164A
http://onsemi.com
6
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a dataenable input. When only one serial input is
used, the other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positivegoing transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
QA QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
ActiveLow, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flipflops and sets
Outputs QA QH to the low level state.
SWITCHING WAVEFORMS
tf
VCC
GND
90%
50%
10%
tw
tPLH
tPHL
CLOCK
Q
tTLH
tTHL
Figure 1.
RESET
trec
Figure 2.
tr
1/fmax
90%
50%
10%
VCC
GND
VCC
GND
Q
CLOCK
50%
tPHL
tw
A1 OR A2
Figure 3.
VCC
GND
VCC
GND
50%
CLOCK
tsu
th
VALID
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
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