TIMING REQUIREMENTS (Input tr = t" />
參數(shù)資料
型號(hào): MC74HC165AFG
廠(chǎng)商: ON Semiconductor
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 0K
描述: IC SHIFT REGISTER 8BIT 16-SOEIAJ
標(biāo)準(zhǔn)包裝: 50
系列: 74HC
邏輯類(lèi)型: 移位寄存器
輸出類(lèi)型: 差分
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
功能: 并行或串行至串行
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOEIAJ
包裝: 管件
MC74HC165A
http://onsemi.com
5
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
tsu
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
th
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)
2.0
3.0
4.5
6.0
5
5
5
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)
2.0
3.0
4.5
6.0
5
5
5
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)
2.0
3.0
4.5
6.0
5
5
5
ns
trec
Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tw
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
tw
Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
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