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參數資料
| 型號： | MC74HC354DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| 中文描述： | HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-20 |
| 文件頁數： | 3/9頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MC74HC354DW |
MC54/74HC354
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Unit
Guaranteed Limit
V
Condition
Parameter
≤
125
°
C
≤
85
°
C
–55 to 25
°
C
VCC
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±
0.5
±
5.0
±
10.0
μ
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
μ
A
6.0
8
80
160
μ
A
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
V
Guaranteed Limit
Unit
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
tPLH,
tPHL
Maximum Propagation Delay, D0–D7 to Y or Y
(Figures 2 and 6)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
tPLH,
tPHL
Maximum Propagation Delay, Data–Latch Enable to Y or Y
(Figures 3 and 6)
2.0
4.5
6.0
260
52
44
325
65
55
390
78
66
ns
tPLH,
tPHL
Maximum Propagation Delay, A0–A2 to Y or Y
(Figures 2 and 6)
2.0
4.5
6.0
270
54
46
340
68
58
405
81
69
ns
tPLH,
tPHL
Maximum Propagation Delay, Address–Latch Enable to Y or Y
(Figures 3 and 6)
2.0
4.5
6.0
270
54
46
340
68
58
405
81
69
ns
tPLZ,
tPHZ
Maximum Propagation Delay, OE1–OE3 to Y or Y
(Figures 4 and 7)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPZL,
tPZH
Maximum Propagation Delay, OE1–OE3 to Y or Y
(Figures 4 and 7)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 6)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Cin
Cout
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High Impedance
State)
15
15
15
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
48
pF
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