參數(shù)資料
    型號: MC74HC373ADWR2
    廠商: ON SEMICONDUCTOR
    元件分類: 通用總線功能
    英文描述: PNP Epitaxial Silicon Transistor
    中文描述: HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
    封裝: SOIC-20
    文件頁數(shù): 1/8頁
    文件大?。?/td> 202K
    代理商: MC74HC373ADWR2
    SEMICONDUCTOR TECHNICAL DATA
    1
    REV 7
    Motorola, Inc. 1997
    3/97
    High–Performance Silicon–Gate CMOS
    The MC54/74HC373A is identical in pinout to the LS373. The device
    inputs are compatible with standard CMOS outputs; with pullup resistors,
    they are compatible with LSTTL outputs.
    These latches appear transparent to data (i.e., the outputs change
    asynchronously) when Latch Enable is high. When Latch Enable goes low,
    data meeting the setup and hold time becomes latched.
    The Output Enable input does not affect the state of the latches, but when
    Output Enable is high, all device outputs are forced to the high–impedance
    state. Thus, data may be latched even when the outputs are not enabled.
    The HC373A is identical in function to the HC573A which has the data
    inputs on the opposite side of the package from the outputs to facilitate PC
    board layout.
    The HC373A is the non–inverting version of the HC533A.
    Output Drive Capability: 15 LSTTL Loads
    Outputs Directly Interface to CMOS, NMOS and TTL
    Operating Voltage Range: 2.0 to 6.0 V
    Low Input Current: 1.0
    μ
    A
    High Noise Immunity Characteristic of CMOS Devices
    In Compliance with the Requirements Defined by JEDEC Standard
    No. 7A
    Chip Complexity: 186 FETs or 46.5 Equivalent Gates
    LOGIC DIAGRAM
    DATA
    INPUTS
    D0
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    18
    17
    14
    13
    8
    7
    4
    3
    1
    OUTPUT ENABLE
    19
    Q0
    Q1
    Q2
    Q3
    Q4
    Q5
    Q6
    Q7
    16
    15
    12
    9
    6
    5
    2
    PIN 20 = VCC
    PIN 10 = GND
    NONINVERTING
    OUTPUTS
    11
    LATCH ENABLE
    Internal Gate Count*
    * Equivalent to a two–input NAND gate.
    46.5
    ea
    PIN ASSIGNMENT
    Q2
    D1
    D0
    Q0
    OUTPUT
    ENABLE
    GND
    Q3
    D3
    D2
    Q1
    5
    4
    3
    2
    1
    10
    9
    8
    7
    6
    14
    15
    16
    17
    18
    19
    20
    11
    12
    13
    Q6
    D6
    D7
    Q7
    VCC
    LATCH
    ENABLE
    Q4
    D4
    D5
    Q5
    FUNCTION TABLE
    Inputs
    Latch
    Enable
    Output
    Output
    Enable
    D
    Q
    L
    L
    L
    H
    H
    H
    L
    X
    H
    L
    X
    X
    H
    L
    No Change
    Z
    X = Don’t Care
    Z = High Impedance
    DW SUFFIX
    SOIC PACKAGE
    CASE 751D–04
    N SUFFIX
    PLASTIC PACKAGE
    CASE 738–03
    ORDERING INFORMATION
    MC54HCXXXAJ
    MC74HCXXXAN
    MC74HCXXXADW
    MC74HCXXXASD
    MC74HCXXXADT
    Ceramic
    Plastic
    SOIC
    SSOP
    TSSOP
    DT SUFFIX
    TSSOP PACKAGE
    CASE 948E–02
    J SUFFIX
    CERAMIC PACKAGE
    CASE 732–03
    1
    20
    1
    20
    SD SUFFIX
    SSOP PACKAGE
    CASE 940C–03
    1
    20
    1
    20
    1
    20
    相關(guān)PDF資料
    PDF描述
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    MC74HC374A Octal 3-State Non-Inverting D Flip-Flop
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    MC74HC373ADWR2G 功能描述:閉鎖 2-6V Transparent Non-Inverting RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
    MC74HC373AF 功能描述:閉鎖 2-6V Transparent RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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