DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed L" />
參數(shù)資料
型號: MC74HC373AFELG
廠商: ON Semiconductor
文件頁數(shù): 4/9頁
文件大小: 0K
描述: IC LATCH TRANSP OCT 3ST 20SOEIAJ
產(chǎn)品變化通告: 1Q2012 Discontinuation 30/Mar/2012
標準包裝: 2,000
系列: 74HC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 6 V
獨立電路: 1
延遲時間 - 傳輸: 21ns
輸出電流高,低: 7.8mA,7.8mA
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
供應商設備封裝: SOEIAJ-20
包裝: 帶卷 (TR)
MC74HC373A
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to 25_C
v 85_C
v 125_C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL
Maximum LowLevel Output
Voltage
Vin = VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
V
Vin = VIL
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.33
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum ThreeState
Leakage Current
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
tPLH
tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
140
90
28
24
175
120
35
30
210
140
42
36
ns
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
15
15
15
pF
CPD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, VCC = 5.0 V
pF
36
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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