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參數(shù)資料
| 型號： | MC74HC393N |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Operational Amplifier; Package: DIP; No of Pins: 8; Container: Rail |
| 中文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 196K |
| 代理商： | MC74HC393N |
MC54/74HC393
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 3)
4.5
27
18
6.0
20
22
31
tPLH,
Maximum Propagation Delay, Clock to Q2
2.0
190
240
26
285
ns
tPHL
(Figures 1 and 3)
4.5
48
72
6.0
49
60
74
tPHL
Maximum Propagation Delay, Reset to any Q
2.0
6.0
165
28
205
62
250
43
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
75
15
35
110
22
ns
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
95
19
CPD
Power Dissipation Capacitance (Per Counter)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
40
pF
Symbol
Parameter
V
Guaranteed Limit
VCC
– 55 to
25 C
125 C
trec
Minimum Recovery Time, Reset Inactive to Clock
2.0
6.0
50
9
85 C
75
13
Unit
ns
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
80
16
100
65
11
120
24
ns
(Figure 2)
4.5
6.0
25
21
20
38
32
tr, tf
Maximum Input Rise and Fall Times
2.0
6.0
1000
400
1000
400
31
26
1000
400
ns
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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