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參數(shù)資料
| 型號： | MC74HC4002 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-input NOR Gate |
| 中文描述： | 雙4輸入或非門 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 138K |
| 代理商： | MC74HC4002 |
MC74HC4002
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
24
36
6 0
13
30
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
26
pF
EXPANDED LOGIC DIAGRAM
(1/2 of the Device)
A
B
Y
C
D
Figure 1.
tf
tr
VCC
GND
90%
50%
10%
90%
50%
10%
INPUT
A, B, C, OR D
OUTPUT Y
tPHL
tPLH
tTHL
tTLH
* Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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