參數(shù)資料
型號： MC74HC4040AD
廠商： ON SEMICONDUCTOR
元件分類： 通用總線功能
英文描述： Dual Operational Amplifier; Package: SOIC; No of Pins: 8; Container: Rail
中文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 3/8頁
文件大小： 215K
代理商： MC74HC4040AD
MC54/74HC4040A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Unit
Guaranteed Limit
V
Condition
Parameter
≤
125
°
C
≤
85
°
C
–55 to 25
°
C
VCC
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
ICC
Maximum Input Leakage Current
Vin = VCC or GND
Vin = VCC or GND
Iout = 0
μ
A
6.0
±
0.1
±
1.0
±
1.0
μ
A
Maximum Quiescent Supply
Current (per Package)
6.0
4
40
160
μ
A
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
V
Guaranteed Limit
Unit
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
15
30
50
9.0
14
28
45
8.0
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q1*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
96
63
31
25
106
71
36
30
115
88
40
35
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
45
30
30
26
52
36
35
32
65
40
40
35
ns
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
69
40
17
14
80
45
21
15
90
50
28
22
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
* For TA = 25
°
C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns
VCC = 6.0V: tP = [24.4 + 12 (n–1)] ns
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
31
pF
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