參數(shù)資料
型號: MC74HC4040AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 12-Stage Binary Ripple Counter
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 1/8頁
文件大小: 215K
代理商: MC74HC4040AN
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master–slave flip–flops. The output of each
flip–flop feeds the next and the frequency at each output is half of that of
the preceding one. The state counter advances on the negative–going
edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
9
7
6
5
3
2
4
13
12
14
Clock
10
Reset
11
Pin 16 = VCC
Pin 8 = GND
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
Q11
Q10
Q8
Q9
Reset Clock
Q1
Q12
Q6
Q5
Q7
Q4
Q3
Q2
GND
Pinout: 16–Lead Plastic Package
(Top View)
Q11
Q12
15
1
FUNCTION TABLE
Clock
Reset
Output State
X
L
L
H
No Charge
Advance to Next State
All Outputs Are Low
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
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