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參數(shù)資料
| 型號(hào)： | MC74HC4538ANG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIVIBRATOR DUAL 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 74HC |
| 邏輯類型： | 單穩(wěn)態(tài) |
| 獨(dú)立電路： | 2 |
| 施密特觸發(fā)器輸入： | 是 |
| 傳輸延遲： | 30ns |
| 輸出電流高，低： | 5.2mA，5.2mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-DIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1123 (CN2011-ZH PDF) |
| 其它名稱： | MC74HC4538ANGOS |
MC74HC4538A
http://onsemi.com
9
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 4, 12)
Positiveedge trigger inputs. A risingedge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.
B1, B2 (Pins 5, 11)
Negativeedge trigger inputs. A fallingedge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A1 or A2 input.
Reset 1, Reset 2 (Pins 3, 13)
Reset inputs (active low). When a low level is applied to
one of these pins, the Q output of the corresponding
multivibrator is reset to a low level and the Q output is set to
a high level.
CX1/RX1 and CX2/RX2 (Pins 2 and 14)
External timing components. These pins are tied to the
common points of the external timing resistors and
capacitors (see the Block Diagram). Polystyrene capacitors
are recommended for optimum pulse width control.
Electrolytic capacitors are not recommended due to high
leakages associated with these type capacitors.
GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.
OUTPUTS
Q1, Q2 (Pins 6, 10)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
the external timing components, RX and CX.
Q1, Q2 (Pins 7, 9)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A
or the B input. These outputs are the inverse of Q1 and Q2.
+
+
RxCx
VCC
M1
2 k
W
M3
M2
A
B
RESET
POWER
ON
RESET
RESET LATCH
TRIGGER CONTROL
RESET CIRCUIT
TRIGGER
CONTROL CIRCUIT
OUTPUT
LATCH
UPPER
REFERENCE
CIRCUIT
Vre,
UPPER
LOWER
REFERENCE
CIRCUIT
Vre,
LOWER
Q
C
CB
Q
R
VCC
Figure 11. Logic Detail (1/2 the Device)
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