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參數(shù)資料
| 型號： | MC74HC597ADTR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 149K |
| 代理商： | MC74HC597ADTR2G |
MC74HC597A
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle), Shift Clock
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QH
2.0
3.0
4.5
6.0
175
100
40
30
225
110
50
40
275
125
60
50
ns
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to QH
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPHL
Maximum Propagation Delay, Reset to QH
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
—
10
pF
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
pF
40
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Activelow shift register reset. A low level
applied to this input resets the shift register to a low level,
but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A lowtohigh transition on this
input shifts data on the Serial Data Input into the shift
register and data in stage H is shifted out QH, being
replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A lowtohigh transition on this input loads
the parallel data on inputs AH into the input latch.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last
stage of the shift register.
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