TIMING REQUIREMENTS (Input tr = t" />
參數(shù)資料
型號(hào): MC74HC597ADTR2G
廠商: ON Semiconductor
文件頁數(shù): 9/12頁
文件大小: 0K
描述: IC SHIFT REGISTER 8-BIT
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 移位寄存器
輸出類型: 標(biāo)準(zhǔn)
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
功能: 串行至并行
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
MC74HC597A
http://onsemi.com
6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
tsu
Minimum Setup Time, Parallel Data inputs AH to Latch Clock
(Figure 7)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tsu
Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 8)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 9)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
th
Minimum Hold Time, Latch Clock to Parallel Data Inputs AH
(Figure 7)
2.0
3.0
4.5
6.0
15
10
2
20
15
3
30
25
5
4
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 8)
2.0
3.0
4.5
6.0
2
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tw
Minimum Pulse Width, Latch Clock and Shift Clock
(Figures 3 and 4)
2.0
3.0
4.5
6.0
60
35
12
10
70
40
15
13
80
45
19
16
ns
tw
Minimum Pulse Width, Reset
(Figure 5)
2.0
3.0
4.5
6.0
60
35
12
10
70
40
15
13
80
45
19
16
ns
tw
Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 6)
2.0
3.0
4.5
6.0
60
35
12
10
70
40
15
13
80
45
19
16
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 3)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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