參數(shù)資料
型號: MC74HC7266AD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: SMPS Controller
中文描述: HC/UH SERIES, QUAD 2-INPUT XNOR GATE, PDSO14
封裝: PLASTIC, SOIC-14
文件頁數(shù): 3/6頁
文件大小: 137K
代理商: MC74HC7266AD
MC74HC7266A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
0.1
|Iout|
20
μ
A
Voltage
0.1
4.5
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
0.26
±
0.1
0.1
Vin = VIH or VIL
|Iout|
|Iout|
|Iout|
6.0
1
0.33
0.40
Iin
ICC
Maximum Quiescent Supply
Maximum Input Leakage Current
Vin = VCC or GND
Vin = VCC or GND
6.0
±
1.0
±
1.0
μ
A
6.0
10
40
μ
A
AC ELECTRICAL CHARACTERISTICS
( CL = 50 pF, Input tr = tf = 6 ns)
b l
V
20
Guaranteed Limit
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
– 55 to
6.0
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
4.5
15
25
25
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
19
22
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
33
pF
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 1. Switching Waveforms
Figure 2. Test Circuit
OUTPUT Y
INPUT
A OR B
90%
50%
10%
tTLH
tTHL
tPLH
tPHL
tr
tf
GND
VCC
90%
50%
10%
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