參數(shù)資料
型號: MC74HC73ADR2G
廠商: ON Semiconductor
文件頁數(shù): 1/7頁
文件大小: 0K
描述: IC DUAL J-K FLPFLP W/REST 14SOIC
標準包裝: 2,500
系列: 74HC
功能: 復位
類型: JK 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 2
頻率 - 時鐘: 35MHz
延遲時間 - 傳輸: 21ns
觸發(fā)器類型: 負邊沿
輸出電流高,低: 5.2mA,5.2mA
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2013
July, 2013 Rev. 9
1
Publication Order Number:
MC74HC73/D
MC74HC73A
Dual J-K Flip-Flop with
Reset
HighPerformance SiliconGate CMOS
The MC74HC73A is identical in pinout to the LS73. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flipflop is negativeedge clocked and has an activelow
asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a
different pinout.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 92 FETs or 23 Equivalent Gates
These are PbFree Devices
PIN ASSIGNMENT
FUNCTION TABLE
LOGIC DIAGRAM
PIN 4 = VCC
PIN 11 = GND
RESET 2
K2
CLOCK 2
J2
RESET 1
K1
CLOCK 1
J1
Q2
Q1
14
1
3
2
7
5
10
6
12
13
9
8
11
12
13
14
8
9
10
5
4
3
2
1
7
6
K2
GND
Q1
J1
Q2
VCC
K1
RESET 1
CLOCK 1
J2
RESET 2
CLOCK 2
Inputs
Outputs
Reset Clock
J
K
Q
L
XXX
L
H
L
No Change
HL
H
L
H
HH
L
H
L
H
Toggle
H
L
X
No Change
H
X
No Change
H
X
No Change
http://onsemi.com
MARKING
DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Package
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOIC14
D SUFFIX
CASE 751A
14
1
HC73AG
AWLYWW
1
14
HC
73A
ALYWG
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
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PDF描述
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