參數(shù)資料
型號: MC74HC73N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual J-K Flip-Flop with Reset
中文描述: HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
封裝: PLASTIC, DIP-14
文件頁數(shù): 1/5頁
文件大?。?/td> 170K
代理商: MC74HC73N
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC73 is identical in pinout to the LS73. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip flop is negative–edge clocked and has an active–low asynchro-
nous reset.
The MC74HC73 is identical in function to the HC107, but has a different
pinout.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAM
PIN 4 = VCC
PIN 11 = GND
RESET 2
K2
CLOCK 2
J2
RESET 1
K1
CLOCK 1
J1
Q2
Q2
Q1
Q1
14
1
3
2
7
5
10
6
12
13
9
8
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Clock
Outputs
Q
Reset
J
K
Q
L
H
H
H
H
H
H
H
X
X
L
L
H
H
X
X
X
X
L
H
L
H
X
X
X
L
H
No Change
L
H
Toggle
No Change
No Change
No Change
H
L
L
H
11
12
13
14
8
9
10
5
4
3
2
1
7
6
K2
GND
Q1
Q1
J1
Q2
Q2
VCC
K1
RESET 1
CLOCK 1
J2
RESET 2
CLOCK 2
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
1
14
1
14
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