DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Param" />
參數(shù)資料
型號(hào): MC74HC74ANG
廠商: ON Semiconductor
文件頁(yè)數(shù): 3/9頁(yè)
文件大小: 0K
描述: IC FLIP FLOP DUAL SET/RST 14DIP
標(biāo)準(zhǔn)包裝: 500
系列: 74HC
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類(lèi)型: D 型
輸出類(lèi)型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 35MHz
延遲時(shí)間 - 傳輸: 17ns
觸發(fā)器類(lèi)型: 正邊沿
輸出電流高,低: 5.2mA,5.2mA
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 通孔
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1122 (CN2011-ZH PDF)
其它名稱(chēng): MC74HC74ANGOS
MC74HC74A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.33
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
2.0
20
80
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
17
125
90
25
21
150
120
30
26
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
18
130
95
26
22
160
130
32
27
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
CPD
Power Dissipation Capacitance (Per FlipFlop)*
Typical @ 25°C, VCC = 5.0 V
pF
32
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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