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參數(shù)資料
| 型號(hào)： | MC74HC85 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4-Bit Magnitude Comparator |
| 中文描述： | 4位數(shù)值比較 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MC74HC85 |
MC74HC85
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
or A < B
4.5
6.0
46
39
69
59
tPLH,
Maximum Propagation Delay, Inputs A or B to Output A = B
2.0
200
250
58
49
300
ns
tPHL
(Figures 1 and 2)
4.5
6.0
35
30
53
45
tPLH,
Maximum Propagation Delay, Inputs A>B or A = B to Output A < B
2.0
175
220
44
37
265
ns
tPHL
(Figures 1 and 2)
4.5
6.0
29
25
44
38
tTLH,
Maximum Output Transition Time, Any Output
2.0
75
36
31
110
ns
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
95
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
50
pF
Figure 1. Switching Waveforms
10%
10%
90%
50%
950%
50%
tr
tf
INPUTS
OUTPUTS
tPLH
tPHL
tPLH
tPHL
tTHL
tTLH
OUTPUTS
VCC
GND
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
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