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| 型號(hào)： | MC74HCT138ADT |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs |
| 中文描述： | HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 218K |
| 代理商： | MC74HCT138ADT |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
!$# &!
%# # $#"
High–Performance Silicon–Gate CMOS
The MC74HCT138A is identical in pinout to the LS138. The HCT138A
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The HCT138A decodes a three–bit Address to one–of–eight active–lot
outputs. This device features three Chip Select inputs, two active–low and
one active–high to facilitate the demultiplexing, cascading, and chip–select-
ing functions. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output; one of the Chip Selects is
used as a data input while the other Chip Selects are held in their active
states.
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
μ
A
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
LOGIC DIAGRAM
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
CS1
CS2
A0
A1
A2
ACTIVE–LOW
OUTPUTS
ADDRESS
INPUTS
CS3
CHIP–
SELECT
INPUTS
5
4
6
PIN 16 = VCC
Design Criteria
Value
Units
Speed Power Product
.0075
pJ
*Equivalent to a two–input NAND gate.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
CS2
A2
A1
Y7
CS1
CS3
GND
Y3
Y2
Y1
Y0
VCC
Y5
Y4
Y6
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
MC74HCTXXXADT
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
Inputs
Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
FUNCTION TABLE
H = high level (steady state)
L = low level (steady state)
X = don’t care
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